1. Field of the Invention
The present invention relates to a synchronous DRAM (dynamic random access memory) for synchronizing an internal clock with an externally generated system clock signal, and in particular, to an internal clock signal generator for synchronous DRAM operating with a reduced current consumption.
2. Description of the Related Art
In general, an internal clock signal generator functions as a buffer between a system and a memory chip operating under different voltages. That is, the internal clock generator generates an internal clock signal of a CMOS (Complementary Metal Oxide Semiconductor) level synchronized with an external system clock of a TTL (Transistor Transistor Logic) level generated from the system. It is advantageous to synchronize the internal clock with the system clock in order to define a time point at which the external clocks such as RAS0, CAS0 RAS, CAS, and WE (WE 0received from the exterior of the chip) are applied into the chip, and further to define an output time point.
In operation, a synchronous DRAM generates an internal clock signal in response to the system clock signal, and the internal clock becomes a reference signal in writing and reading data into/from a selected memory element. In order to generate the internal clock signal, the synchronous DRAM generally employs a clock buffer which responds to the externally generated system clock signal. Use of such a clock buffer delays the system clock signal, resulting in a phase difference between the system clock and the internal clock. This delay is undesirable for the proper operation of the memory circuit.
One conventional method for removing the phase difference uses a phase locked loop (PLL) and a delay locked loop (DLL) to minimize the skew between the system clock and the internal clock. This method requires a long time to remove the phase difference which causes an increase of an overall stand-by current even during a stand-by mode at which the device is inactive. Thus, such a conventional method is not suitable for use with a high-speed synchronous DRAM.
Accordingly, an improved method has been developed using a digital delay locked loop having a plurality of unit delay circuits and phase detection circuits as shown in FIG. 1. In this improved method, a clock buffer BDC generates a clock signal PCLK.sub.-- M delayed for a predetermined time in response to an external clock signal CLK. The clock signal PCLK.sub.-- M is coupled to a main delay circuit MDC, phase detection circuits PDCi (i=a natural number), and a unit delay circuit BUD1. The main delay circuit MDC has the same time delay value as that of the clock buffer BDC, and generates a clock signal MD with a time delay in response to the clock signal PCLK.sub.-- M. A plurality of unit delay circuits FUD1-FUDn having the same time delay value are coupled, as a second synchronous delay line, in series to an output terminal of the main delay circuit MDC. The unit delay circuits FUD1-FUDn generate clock signals D1-Dn, respectively. The phase detection circuits PDC1-PDCi (i=n+1, i.e., the number of phase detection circuits is larger by one than that of the unit delay circuits) latch the received clock signals MD and D1-Dn in response to the clock signal PCLK.sub.-- M. Phase detection circuits PDC1-PDCi then compare outputs of the phase detection circuits of the preceding stages with the latched signals, to generate a signal Fj (representing an unspecified signal). The unspecified signal Fj is activated only when the output of the phase detection circuit and the latched signal are in phase. The phase detection circuits PDC1-PDCi are activated and deactivated according to input signals T1-Ti. That is, the signals T1-Ti disable the phase detection circuits at the following stages of a phase detection circuit which generates the signal Fj which is activated when the external clock CLK and the internal clock PCLK are in phase.
A plurality of the unit delay circuits BUD1-BUDn are coupled in series, as a first synchronous delay line, to an output terminal of the clock buffer BDC and generate clock signals D1'-Dn', respectively. Switches SW1-SWi are respectively coupled between an output terminal of the internal clock signal PCLK and input terminals of the unit delay circuits BUD1-BUDn, whereby a switching operation of the switches SW1-SWi is controlled by the corresponding signals F1-Fi.
FIG. 2 is a diagram for illustrating an output timing of the internal clock generator shown in FIG. 1.
Referring to FIGS. 1 and 2, upon receiving the external system clock signal CLK received via an input terminal of the internal clock generator, the clock buffer BDC generates the clock signal PCLK.sub.-- M with a predetermined time delay. The main delay circuit MDC having a time delay value corresponding to the time delay value of the clock buffer BDC further delays the clock signal PCLK.sub.-- M to generate the clock signal MD. Further, the clock signal PCLK.sub.-- M is applied to the input terminals of a plurality of phase detection circuits PDC1-PDCi (i=n+1, where n represents the number of the unit delay circuits) and an input terminal of a first unit delay circuit BUD1 among the unit delay circuits BUD1-BUDn constituting the first synchronous delay line.
Upon receiving the clock signal MD, the unit delay circuits FUD1-FUDn, coupled in series to an output terminal of the main delay circuit MDC, generate time-delayed clock signals D1-Dn, respectively. Here, the respective unit delay circuits FUD1-FUDn have the same time delay value. Further, the respective unit delay circuits BUD1-BUDn, constituting the first synchronous delay line, have the same time delay value as that of the unit delay circuits FUD1-FUDn.
The clocks signals MD and D1-Dn are applied to input terminals of the corresponding phase detection circuits PDC1-PDCi, and are respectively latched in these circuits under the control of the clock signal PCLK.sub.-- M. The latched clock signal is compared with a signal output from the phase detection circuit at a preceding stage of a phase detection circuit which performs a comparison operation. If the latched clock signal and the output signal of the phase detection circuit at the preceding stage are in phase, the clock signal Fi is activated. If the clock signal Fi is activated, only the switch SWi associated with the activated clock signal Fi is turned on. The remaining switches maintain a turn-off state. A time-delayed clock signal Dn' generated via the turned-on switch SWi is used for the internal clock signal PCLK where the internal clock signal PCLK is now synchronized with the external clock signal CLK.
As shown in FIG. 2, it takes a total of two complete cycles of the external clock signal CLK for the internal clock signal PCLK to be fully synchronized with the external clock signal CLK. Accordingly, after a lapse of the two cycles of the external clock signal CLK, the internal clock signal PCLK is generated in phase with the external clock signal CLK without the time delay difference. That is, an internal clock generator that uses the technique shown in FIGS. 1 and 2 is an improvement over the conventional phase locked loop or delay locked loop method because the internal clock generator is synchronized with the external clock PCLK much quicker.
Though an improvement in the art, the internal clock generator shown in FIGS. 1 and 2 still has many disadvantages. FIG. 3 shows a detailed circuit diagram of the internal clock generator shown in FIG. 1, connected between the input terminal of the external clock CLK and an output line of the internal clock PCLK, in which the time delay value of the clock buffer BDC is divided. That is, the time delay value of the main delay circuit MDC is identical to the time delay of a clock buffer BDC1 (not shown) plus the time delay of internal delay circuit ID. The clock buffer BDC1 is coupled to an input terminal of the external clock CLK, and the internal delay circuit ID is coupled to the output terminals of the switches SW1-SWi,
In one design, the clock buffer BDC can have the same time delay value as that of the main delay circuit MDC without dividing the time delay value thereof. Further, the internal clock generator is connected between the output terminal of the clock buffer BDC1 and the main delay circuit MDC, and includes a logic controller controlled by a switching control signal PSDLE which is activated during read and write operations.
As shown in FIG. 3A, the logic controller includes a NAND gate NG4 which receives the clock signal PCLK.sub.-- M and the switching control signal PSDLE at two input terminals thereof. The logic controller further includes a NAND gate NG3 which receives an inverse PCLK.sub.-- M clock signal output of an inverter 123 and the switching control signal PSDLE at two input terminals thereof. An output terminal of the NAND gate NG4 is coupled to input terminals of the phase detection circuits PDC1-PDCi. The output terminal of the NAND gate NG3 is coupled to the first synchronous delay line and an input terminal of the main delay circuit MDC.
Following is a description of the construction and operation of a conventional internal clock generator, with reference to FIGS. 3A/3B. The clock buffer BDC1 which receives the external clock CLK is composed of seres-connected inverters 11-14 (not shown). The main delay circuit MDC is composed of inverters 15-110 connected in series to the output terminal of the clock buffer BDCI for generating the clock signal PCLK.sub.-- M. Further, in order to have the same time delay value as that of the main delay circuit MDC, the time delay value of the internal delay circuit ID is added to the time delay value of the clock buffer BDC1. Such an internal delay circuit ID is coupled to an output line of the internal clock PCLK, and is composed of series-connected inverters 121 and 122. It is noted that the delay imparted by the clock buffer BDC1 plus the delay imparted by the internal delay circuit ID is equal to the delay imparted by the main delay circuit MDC. Each of the unit delay circuits FUD1-FUDn and BUD1-BUDn are delayed equally by series-connected inverters 111 and 112. Further, the respective phase detection circuits PDC1-PDCi, are composed of transmission gates TG1 and TG2, latch circuits L1 and L2, inverters 116 and 119, and NAND gates NG1 and NG2.
Following is a description of one phase detection circuit PDC1 out of the phase detection circuits PDC1-PDCi, by way of example. The transmission gate TG1, constituting the phase detection circuit PDC1, is composed of a PMOS transistor and an NMOS transistor. A gate of the PMOS transistor is switched in response to the clock signal PCLK.sub.-- M. A gate of the NMOS transistor is switched in response to the inverse PCLK.sub.-- M clock signal generated from an inverter NAND gate NG4 connected between the output terminal of the clock buffer BDC1 and the input terminal of the phase detection circuit PDC1.
The phase detection circuits PDC1-PDCi temporarily store the signal output MD or Dn from the second synchronous delay line into a latch L1 by way of the transmission gate TG1, whereby TG1 is switched in response to the high level transition of the clock PCLK.sub.-- M. The latch circuit L1 is coupled to an output terminal of the transmission gate TG1, and includes two inverters 114 and 115. The inverter 116 for inverting the signal latched at the latch L1 is coupled between the latch L1 and an input terminal of the transmission gate TG2. The transmission gate TG2 performs a switching operation in response to the complementary PCLK.sub.-- M clock. That is, a gate of the PMOS transistor constituting the transmission gate TG2 is switched in response to the clock PCLK.sub.-- M. Furthermore, a gate of the NMOS transistor constituting the transmission gate TG2 is switched in response to the inverse clock signal output from the inverter 113.
The latch L2 has an end connected to an output terminal of the transmission gate TG2, and another end connected to a first input terminal of the NAND gate NG1. A second input terminal of the NAND gate NG1 is coupled to an output Ti of the phase detection circuit PDCi of the preceding stage. In the case of the first phase detection circuit PDC1, the signal T1 applied to a second input terminal of the NAND gate NG1 has a voltage of a predetermined high level.
The switch SW1 is driven when the NAND gate NG2 which receives the signal output from the NAND gate NG1 and the signal T1 generates a low level signal output. The NAND gate NG2 is activated when the two input signals are both at the high level. An output terminal of the NAND gate NG1 is coupled to an inverter 119 for generating the signal T2 for activating the phase detection circuit PDC2 of the following stage. An NMOS transistor NT1 coupled to an end of the latch L1 and an NMOS transistor NT2 coupled to an end of the latch L2 are elements for setting an initial level of the phase detection circuit PDC1. A signal VCCHB which is enabled more quickly than power-up of the device is applied to gates of the NMOS transistors NT1 and NT2. The remaining phase detection circuits PDC2-PDCi have the same construction as the above described phase detection circuit PDC1.
Each of the switches SW1-SWi is coupled to an output terminal of the NAND gate NG2 in the corresponding phase detection circuits PDC1-PDCi. The respective switches SW1-SWi include an inverter 120 coupled to the output terminal of the NAND gate NG2, an NMOS transistor that performs a switching operation according to an inverse signal output from the inverter 120, and a PMOS transistor that performs a switching operation according to a signal output from the NAND gate NG2. The PMOS and NMOS transistors of switches SW1-SWi form a transmission gate TG3 which is connected between an input terminal of the respective unit delay circuits BUD1-BUDn and an input terminal of the internal delay circuit ID.
As illustrated in FIG. 2, when the clock signal PCLK.sub.-- M transits to a high level, the transmission gate TG1 is turned on and the high-level clock signal D11 is applied to the phase detection circuit PDC12. As a result, the input signal T13 (not shown in FIG. 2) of phase detection circuit PDC13 transits from the active high level to the low level, thereby disabling the phase detection circuits PDC13-PDCi of the following stages. That is, the phase detection circuits PDC13-PDCi of the following stages generate the high level via the NAND gate NG2, thereby turning off the switches SW13-SWi. Accordingly, the external clock signal CLK, having passed through the clock buffer BDC1, the unit delay circuits BUD1-BUD11, and the internal delay circuit ID, is used for the internal clock signal PCLK. Such an internal clock signal PCLK is synchronized with the external clock signal CLK without a phase delay difference between them.
The above described internal clock generator must include a great number of the unit delay circuits FUD1-FUDn and BUD1-BUDn, and phase detection circuits PDC1-PDCi. Thus, it can be readily appreciated that the current consumptions of such an internal clock generator is high. Further, in order to secure a low frequency margin, the internal clock generator needs to increase the number of unit delay circuits FUD1-FUDn and BUD1-BUDn, and phase detection circuits PDC1-PDCi, which results in a further increase of the current consumptions.